A New Composite CPU/Memory Model for Predicting Efficiency of Multi-core Processing




Hasan, Khondker

Journal Title

Journal ISSN

Volume Title


IEEE Computer Society


Techniques for predicting the efficiency of multi-core processing associated with a set of tasks with varied CPU and main memory requirements are introduced. Given a set of tasks each with different CPU and main memory requirements, and a multi-core system (which generally has fewer cores than the number of tasks), our goal is to derive equations for upper-and lower-bounds to estimate the efficiency with which the tasks are executed. Prediction of execution efficiency of processes due to CPU and required memory availability is important in the context of making process assignment, load balancing, and scheduling decisions in distributed systems. Input parameters to models include: number of cores, number of threads, CPU usage factor of threads, available memory frames, required amount of memory for each thread, and others. Additionally, a CPU availability average prediction model is introduced from the empirical study for the set of applications that require a single predicted value instead of bounds. Extensive experimental studies and statistical analysis are performed and observed that the proposed efficiency bounds are consistently tight. The model provides a basis of an empirical model for predicting execution efficiency of threads while CPU and memory resources are uncertain. To facilitate scientific and controlled empirical evaluation, real-world benchmark programs with dynamic behavior are employed on UNIX systems that are parameterized by their CPU usage factor and memory requirement.



Composite prediction model, CPU availability, Execution Efficiency, Memory availability, Multi-core processors, Modeling and prediction


Khondker S. Hasan, John Antonio, Sridhar Radhakrishnan,“A New Composite CPU/Memory Model for Predicting Efficiency of Multi-core Processing”, The 20th IEEE International Conference on High Performance Computer Architecture (HPCA-14), Workshop on SoCs, Heterogeneous Architectures and Workloads (SHAW- 5), Sponsored by: IEEE Computer Society, DOI: 10.13140/RG.2.1.3051.9207, Orlando, FL, USA, 15-19 February 2014.