Xiaokun Yang

Permanent URI for this collectionhttps://hdl.handle.net/10657.1/2213

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Dr. Xiaokun Yang is currently an Assistant Professor at the College of Science and Engineering, University of Houston, Clear Lake. He received his Ph.D. from the Department of Electrical and Computer Engineering (ECE), Florida International University (FIU), USA in Spring 2016, his dual M.S. from the Department of ECE at FIU and the Department of Software Engineering at Beihang University, China in 2007.
From 2007 to 2012, he has also worked as a Senior ASIC Design/Layout Engineer at Advanced Micro Devices (AMD), China Electronic Corporation (CEC), and PowerLayer MicroSystems (PLM). His chip tape-out experiences include AMD CPUs/APUs (Kabini, Kaveri, Bonaire, Kryptos, and Samara), 802.11 a/b/g/n MIMO mixed-signal SoCs (CEC TL3 and TL5), and PLM high-definition TV (HDTV) SoCs (PLM3K and PLM5K).

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Browsing Xiaokun Yang by Title

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    An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems
    (2017-10-19) Yang, Xiaokun
    Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual property (IP) cores. The bus architecture can include a control-bus with a single master, such as a microprocessor, and a data-bus with a single slave, such as DMA.
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    A Case Study of Self-Organization Algorithms for High-Efficiency System-on-Chips Integration
    (IEEE Intl. Conf. on Autonomic Computing, 2017-07) Yang, Xiaokun
    As the industry reaps the benefits of Moore's Law and chip designs increase in complexity, System-on-Chip (SoC) integration is becoming intractable with the advent of many new bus or interface protocols. As a case study, this paper proposes a self-organization algorithm for designing high-efficiency SBUS wrappers in order to interconnect third-party Intellectual Properties (IPs) and find a right balance between system performance and resource cost. Field-programmable gate array (FPGA) results show large reduction in our self-integration system's area and energy consumption (77.6% in block tests), compared with the AXI3 SoC. Additionally our proposed work achieves higher valid throughput (up to 1.2×) than the AXI3 implementation.
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    Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure
    (Journal of VLSI Design, 2017-05) Yang, Xiaokun
    This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.
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    Design of A Bio-Feedback Digital System (BFS) Using 33-Step Training Table for Cardio Equipment
    (The 8th Intl. Conference on Applied Human Factors and Ergonomics, 2017-06) Yang, Xiaokun
    In order to efficiently instruct aerobic training on cardio equipment, this paper proposes a secure biofeedback digital system (BFS) with a 33-step training table. As a case study, the system is simulated using Virtex5-110t filed-programming gate array (FPGA) to run-time monitor body information and feedback guide the exercise intensity. Experimental results show that the BFS system can be effectively implemented with 11352 slices cost and 618 mW dynamic power consumption. Additionally, the throughput can reach 2.30 Gbps for cipher tests.
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    Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)
    (The 22nd Asia and South Pacific Design Automation Conference, 2017-01) Yang, Xiaokun
    This paper proposes a high efficiency data bus (DBUS) for Advanced Encryption Standard (AES) encrypted system-on-chips (SoCs). Using DBUS, the data sequence can be pre-selected for AES encryption/decryption, so that the state buffering and rescheduling overhead can be reduced. FPGA results show that the DBUS based design lowers the dynamic energy to 66.93%, and achieves up to 1.30 times higher valid throughput compared with the Advanced eXensible Interface (AXI) based implementation.
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    Energy Minimization for On-Line Real-Time Scheduling with Reliability Awareness
    (Elsevier Journal of Systems and Software, 2017-05) Yang, Xiaokun
    Under current development of semiconductor technology, there is an exponential increase in transistor density on a single processing chip. This aggressive transistor integration significantly boosts the computing performance. However, it also results in a power explosion, which immediately decreases the system reliability. Moreover, some well-known power/energy reduction techniques, i.e. Dynamic Voltage and Frequency Scaling (DVFS), can cause adverse impact on system reliability. How to effectively manage the power/energy consumption, meanwhile keep the system reliability under control, is critical for the design of high performance computing systems. In this paper, we present an online power management approach to minimize the energy consumption for single processor real-time scheduling under reliability constraint. We formally prove that the proposed algorithm can guarantee the system reliability requirement. Our simulation results show that, by exploiting the run-time dynamics, the proposed approach can achieve more energy savings over previous work under reliability constraint.
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    Establishing a BLE Mesh Network using Fabricated CSRmesh Devices
    (The 2nd ACM/IEEE Symposium on Edge Computing, 2017-10) Yang, Xiaokun
    In this demo we fabricate 4 development boards using the APlix CSR1010 modules and then establish a Bluetooth Low Energy (BLE) mesh network, which is suitable for power-limited and low-complexity IoT applications with low-priority and infrequent data traffic. In addition to the basic operations such as sensing and actuating devices, this demo also shows a BLE star-mesh integration topology to extend the connectivity range to cover 4 laboratories.
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    Exploiting Energy-Quality (E-Q) Tradeoffs: A Case Study of An Approximate FPGA Design
    (IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018) Yang, Xiaokun
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    Improving AES Core Performance via An Advanced IBUS Protocol
    (ACM Journal on Emerging Technologies in Computing, 2018-01) Yang, Xiaokun
    Security is becoming a de-facto requirement of System-on-Chips (SoC), leading up to a significant share of circuit design cost. In this article, we propose an advanced SBUS protocol (ASBUS), to improve the data feeding efficiency of the Advanced Encryption Standard (AES) encrypted circuits. As a case study, the direct memory access (DMA) combined with AES engine and memory controller are implemented as our design-under-test (DUT) using field-programmable gate arrays (FPGA). The results show that our presented ASBUS structure outperforms the AXI-based design for cipher tests. As an example, the 32-bit ASBUS design costs less in terms of hardware resources and achieves higher throughput (1.30 ×) than the 32-bit AXI implementation, and the dynamic energy consumed by the ASBUS cipher test is reduced to 71.27% compared with the AXI test.
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