Parameterizable Design on Convolutional Neural Networks with Chisel Hardware Construction Language
| dc.contributor.advisor | Yang, Xiaokun | |
| dc.contributor.committeeMember | Koc, Hakduran | |
| dc.contributor.committeeMember | Unawala, Ishaq | |
| dc.creator | Madineni, Mukesh Chowdary | |
| dc.date.accessioned | 2023-07-06T18:39:09Z | |
| dc.date.available | 2023-07-06T18:39:09Z | |
| dc.date.created | 2023-05 | |
| dc.date.issued | 2023-04-21 | |
| dc.date.submitted | May 2023 | |
| dc.date.updated | 2023-07-06T18:39:10Z | |
| dc.description.abstract | This thesis presents a parameterizable design generator on convolutional neural networks (CNNs) using Chisel hardware construction language (HCL). Chisel HCL is an open-source embedded domain-specific language (created and maintained by University of California, Berkeley) that inherits the object-oriented feature of Scala for constructing hardware. By parameterizing structural designs such as the streaming width, pooling layer type, and floating-point precision, multiple register-transfer level (RTL) implementations can be created to meet various accuracy and hardware cost requirements. The HCL design can generate the RTL implementations with Verilog, which is synthesizable and implementable on FPGAs (field-programmable gate arrays). The evaluation is based on generated RTL designs including 16-bit, 32-bit, 64-bit, and 128-bit implementations on FPGAs. The experimental results show that the 32-bit design achieves optimal hardware performance when setting the same weights for estimating the quality of results, FPGA slice count, and power dissipation. Although the focus is on CNNs, the approach can be extended to other neural network models for efficient RTL designs. | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | https://hdl.handle.net/10657.1/3033 | |
| dc.language.iso | en | |
| dc.subject | convolutional neural network (CNN) | |
| dc.subject | Chisel HCL | |
| dc.subject | FPGA | |
| dc.subject | register–transfer level | |
| dc.subject | Verilog HDL | |
| dc.title | Parameterizable Design on Convolutional Neural Networks with Chisel Hardware Construction Language | |
| dc.type | Thesis | |
| dc.type.material | text | |
| thesis.degree.grantor | University of Houston-Clear Lake | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science |
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