A Case Study of Self-Organization Algorithms for High-Efficiency System-on-Chips Integration
| dc.contributor.author | Yang, Xiaokun | |
| dc.date.accessioned | 2020-04-20T17:38:52Z | |
| dc.date.available | 2020-04-20T17:38:52Z | |
| dc.date.issued | 2017-07 | |
| dc.description.abstract | As the industry reaps the benefits of Moore's Law and chip designs increase in complexity, System-on-Chip (SoC) integration is becoming intractable with the advent of many new bus or interface protocols. As a case study, this paper proposes a self-organization algorithm for designing high-efficiency SBUS wrappers in order to interconnect third-party Intellectual Properties (IPs) and find a right balance between system performance and resource cost. Field-programmable gate array (FPGA) results show large reduction in our self-integration system's area and energy consumption (77.6% in block tests), compared with the AXI3 SoC. Additionally our proposed work achieves higher valid throughput (up to 1.2×) than the AXI3 implementation. | en_US |
| dc.identifier.citation | X. Yang, Y. Zhang, W. Wen, and M. Fan, "A Case Study of Self-Organization Algorithms for High-Efficiency System-on-Chips Integration," IEEE Intl. Conf. on Autonomic Computing (ICAC 2017) – Workshop on Feedback Computing, Accepted, In Press, July, 2017. | en_US |
| dc.identifier.uri | https://hdl.handle.net/10657.1/2271 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | IEEE Intl. Conf. on Autonomic Computing | en_US |
| dc.subject | bus wrappers, field-programmable gate array (FPGA), IP integration, self-organization, System-onChips(SoC) | en_US |
| dc.title | A Case Study of Self-Organization Algorithms for High-Efficiency System-on-Chips Integration | en_US |
| dc.type | Article | en_US |
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