Tradeoff FPGA Cost of Sobel Implementation Using Approximate Designs



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This dissertation proposes a scalable algorithm for tuning the tradeoff of space, energy, and quality for the implementation on Field-Programmable Gate Array (FPGA). First, an approximate design library including exact and several imprecise designs on adders and subtractors is presented. Using the design library, then six different approximation levels of register-transfer level (RTL) designs on a Sobel edge detection algorithm is created as a case study, in order to demonstrate the advantage of approximate design and develop a specific implementation to save energy and space at the cost of accuracy. Finally, all the designs of the Sobel engine are synthesized in Xilinx Vivado where the comparison between exact design and an array of approximate designs are conducted. Experimental results show that our proposed work achieves the maximum savings of 26% energy, 24% slice count, and 21% of look-up tables (LUTs) at the cost of 1.14% accuracy when images are compared pixel by pixel. In order to further explore the difference between FPGA demonstrations of the exact design and imprecise implementations, all the Sobel cores are integrated with an image processing platform including OV7670 camera, VGA-enabled monitor, and Xilinx Nexys 4 FPGA to show the quality of edge detection images. By integrating the designs of I2C controller, image capture interface, and the VGA master with our proposed Sobel engines, the simulation with Mentor Graphic ModelSim proves the validity of our proposed work.



FPGA, Field Programmable Gate Array, RTL, register transfer level design