A scalable image/video FPGA processing platform with approximate design



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This dissertation presents a scalable image/video platform with approximate computing design on Field-Programmable Gate Array (FPGA). The platform is able to capture images in real time with a low-cost OV7670 camera and display the original, in-process and final results of images on a VGA-interfaced monitor. To make the platform reusable and expandable, the design with Verilog Hardware Description Language (HDL) and the verification environment including six Open Verification Components (OVCs) are provided. Compared to prior works, our proposed work achieves the least FPGA resource cost (753 Look Up Tables (LUTs) and 277 Registers) on the design of a Camera-FPGA-VGA platform. Furthermore, we present a novel approximate design library with FPGA and provide several slice-energy cost solutions corresponding to different application constrains. Specifically three approximations of multipliers and two approximations of adders, along with the exact designs, are presented and integrated as twelve benchmarks to implement RGB to grayscale conversion as a case study. Experimental results show that the minimum slice-energy cost, integrated with approximate#2 adder and approximate#3 multiplier, achieves 25.17% slice-energy saving compared with the exact design by sacrificing the quality of results as 5.69% error for multiplier and 2.85% for adder.