Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)
| dc.contributor.author | Yang, Xiaokun | |
| dc.date.accessioned | 2020-04-16T18:57:55Z | |
| dc.date.available | 2020-04-16T18:57:55Z | |
| dc.date.issued | 2017-01 | |
| dc.description.abstract | This paper proposes a high efficiency data bus (DBUS) for Advanced Encryption Standard (AES) encrypted system-on-chips (SoCs). Using DBUS, the data sequence can be pre-selected for AES encryption/decryption, so that the state buffering and rescheduling overhead can be reduced. FPGA results show that the DBUS based design lowers the dynamic energy to 66.93%, and achieves up to 1.30 times higher valid throughput compared with the Advanced eXensible Interface (AXI) based implementation. | en_US |
| dc.identifier.citation | X. Yang and W. Wen, "Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)," The 22nd Asia and South Pacific Design Automation Conference, (ASP-DAC 2017 - Regular Paper, Acceptance Rate:111/358=31%), PP. 506-511, Jan. 2017. doi>10.1109/ASPDAC.2017.7858373 | en_US |
| dc.identifier.uri | https://hdl.handle.net/10657.1/2259 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The 22nd Asia and South Pacific Design Automation Conference | en_US |
| dc.subject | Ciphers , Engines , Encryption , Timing , Throughput , Protocols | en_US |
| dc.subject | cryptography , field programmable gate arrays , system-on-chip | en_US |
| dc.subject | pre-scheduled data bus design , advanced encryption standard , AES , encrypted system-on-chips , SoC , high efficiency data bus , DBUS , decryption , state buffering , rescheduling overhead , FPGA , AXI based implementation , advanced exensible interface based implementation | en_US |
| dc.title | Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs) | en_US |
| dc.type | Article | en_US |
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