An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems
| dc.contributor.author | Yang, Xiaokun | |
| dc.date.accessioned | 2020-03-31T02:57:38Z | |
| dc.date.available | 2020-03-31T02:57:38Z | |
| dc.date.issued | 2017-10-19 | |
| dc.description.abstract | Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual property (IP) cores. The bus architecture can include a control-bus with a single master, such as a microprocessor, and a data-bus with a single slave, such as DMA. | en_US |
| dc.identifier.citation | X. Yang and J. Andrian, "An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems," US Patent, US20170302438A1, Oct. 19, 2017. | en_US |
| dc.identifier.other | US Patent, US20170302438A1 | |
| dc.identifier.uri | https://hdl.handle.net/10657.1/2215 | |
| dc.language.iso | en_US | en_US |
| dc.title | An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems | en_US |
| dc.type | Other | en_US |
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