Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks

dc.contributor.authorBettayeb, Said
dc.date.accessioned2020-05-04T15:56:03Z
dc.date.available2020-05-04T15:56:03Z
dc.date.issued1995
dc.description.abstractIt is well known that the hypercube has a rich set of good properties, and consequently it has been recognized an ideal structure for parallel computation. Nevertheless, according to the current VLSI technology, the implementation feasibility of the hypercube remains questionable when the size of the hypercube becomes large. Recent research efforts have been concentrated on finding good alternatives to the hypercube. The star graph was shown having many desirable properties of the hypercube, and in several aspects, the star graph is better than the hypercube. However, we observe that the star graph as a network has several disadvantages, compared with the hypercube. In this paper, we propose a class of new networks, the star-hypercube hybrid networks (or the SH networks). The SH network is a simple combination of both the star graph and the hypercube. This class of networks contains the star graph and the hypercube as subclasses. We show that the SH network is an efficient and versatile network for parallel computation, since it shares properties of both the hypercube and the star graph, and remedies several major disadvantages of the hypercube and the star graph. This class of networks provide more flexibility in choosing the size, degree, number of vertices, degree of fault tolerance, etc. in designing massively parallel computing structures feasible for VLSI implementations.en_US
dc.identifier.citation• Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks, (with B. Cong and S.Q. Zheng), VLSI Design, 1995, Vol. 2, No 4, pp. 365-374.en_US
dc.identifier.urihttps://hdl.handle.net/10657.1/2322
dc.publisherVLSI Designen_US
dc.subjectCartesian product networks embedding interconnection networks star graph.en_US
dc.titleTrade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networksen_US
dc.typeArticleen_US

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