Towards High-Throughput and Low-Cost SoC Integration: A Case Study of Scalable Wrapper Designs on FPGAs
| dc.contributor.author | Yang, Xiaokun | |
| dc.date.accessioned | 2020-04-21T17:51:13Z | |
| dc.date.available | 2020-04-21T17:51:13Z | |
| dc.date.issued | 2018 | |
| dc.identifier.citation | X. Yang, L. Wu, H. He, etc., "Towards High-Throughput and Low-Cost SoC Integration: A Case Study of Scalable Wrapper Designs on FPGAs," IET Computers & Digital Techniques (CDT - IF: 0.589), Under Review, 2018. | en_US |
| dc.identifier.uri | https://hdl.handle.net/10657.1/2280 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | IET Computers & Digital Techniques | en_US |
| dc.title | Towards High-Throughput and Low-Cost SoC Integration: A Case Study of Scalable Wrapper Designs on FPGAs | en_US |
| dc.type | Article | en_US |
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