Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure

dc.contributor.author	Yang, Xiaokun
dc.date.accessioned	2020-04-17T17:42:37Z
dc.date.available	2020-04-17T17:42:37Z
dc.date.issued	2017-05
dc.description.abstract	This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.	en_US
dc.identifier.citation	X. Yang, N. Wu, and J. Andrian, "Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure," Journal of VLSI Design, Vol. 2017, Article ID 4914301, PP. 1-7, May 2017. doi>https://doi.org/10.1155/2017/4914301	en_US
dc.identifier.uri	https://hdl.handle.net/10657.1/2266
dc.language.iso	en_US	en_US
dc.publisher	Journal of VLSI Design	en_US
dc.subject	COMPUTER SCIENCE, HARDWARE & ARCHITECTURE	en_US
dc.title	Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure	en_US
dc.type	Article	en_US

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