Unwala, Ishaq2019-02-192019-02-192018-052018-05-02May 2018https://hdl.handle.net/10657.1/1359Functional verification plays a critical role in ensuring that a digital integrated circuit (IC) meets the design specification. Dynamic verification uses a large number of test vectors. To analyze and improve the quality of these test vectors, the technique of mutation testing is used. In mutation testing the design is mutated with a known fault. To verify the quality of the test vectors the mutated design is retested with test vectors. Current mutation operators include arithmetic, logical, or relational operators. These operators mutate functional portion of the design. However, a significant number of design faults are related to signal timing. To mutate the design for signal timing, this research introduces a new operator, time-shift operator. Time-shift operator allows mutation of the signal timing, which allows an improvement in the quality of test vectors. In this research, it is shown that time-shift operator can be used in combination and sequential designs. This research also shows that the time-shift operator can be utilized in both behavioral and gate-level designs. The results of 9 different designs are presented covering all the cases of combination, sequential, behavioral and get-level designs.application/pdfenDigital integrated circuits--TestingIntegrated circuits--VerificationThesis2019-02-19