Yang, Xiaokun2020-03-312020-03-312017-10-19X. Yang and J. Andrian, "An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems," US Patent, US20170302438A1, Oct. 19, 2017.US Patent, US20170302438A1https://hdl.handle.net/10657.1/2215Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual property (IP) cores. The bus architecture can include a control-bus with a single master, such as a microprocessor, and a data-bus with a single slave, such as DMA.en-USOther