Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure
Date
2017-05
Authors
Yang, Xiaokun
Journal Title
Journal ISSN
Volume Title
Publisher
Journal of VLSI Design
Abstract
This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.
Description
Keywords
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Citation
X. Yang, N. Wu, and J. Andrian, "Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure," Journal of VLSI Design, Vol. 2017, Article ID 4914301, PP. 1-7, May 2017. doi>https://doi.org/10.1155/2017/4914301