Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)
Date
2017-01
Authors
Yang, Xiaokun
Journal Title
Journal ISSN
Volume Title
Publisher
The 22nd Asia and South Pacific Design Automation Conference
Abstract
This paper proposes a high efficiency data bus (DBUS) for Advanced Encryption Standard (AES) encrypted system-on-chips (SoCs). Using DBUS, the data sequence can be pre-selected for AES encryption/decryption, so that the state buffering and rescheduling overhead can be reduced. FPGA results show that the DBUS based design lowers the dynamic energy to 66.93%, and achieves up to 1.30 times higher valid throughput compared with the Advanced eXensible Interface (AXI) based implementation.
Description
Keywords
Ciphers , Engines , Encryption , Timing , Throughput , Protocols, cryptography , field programmable gate arrays , system-on-chip, pre-scheduled data bus design , advanced encryption standard , AES , encrypted system-on-chips , SoC , high efficiency data bus , DBUS , decryption , state buffering , rescheduling overhead , FPGA , AXI based implementation , advanced exensible interface based implementation
Citation
X. Yang and W. Wen, "Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)," The 22nd Asia and South Pacific Design Automation Conference, (ASP-DAC 2017 - Regular Paper, Acceptance Rate:111/358=31%), PP. 506-511, Jan. 2017. doi>10.1109/ASPDAC.2017.7858373