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dc.contributor.authorYang, Xiaokun
dc.date.accessioned2020-04-16T18:11:57Z
dc.date.available2020-04-16T18:11:57Z
dc.date.issued2018-01
dc.identifier.citationX. Yang, W. Wen, and M. Fan, "Improving AES Core Performance via An Advanced IBUS Protocol," ACM Journal on Emerging Technologies in Computing (JETC - IF: 0.803), Vol. 14, No. 1, PP. 61-63 , Jan. 2018. doi>10.1145/3110713en_US
dc.identifier.urihttps://hdl.handle.net/10657.1/2258
dc.description.abstractSecurity is becoming a de-facto requirement of System-on-Chips (SoC), leading up to a significant share of circuit design cost. In this article, we propose an advanced SBUS protocol (ASBUS), to improve the data feeding efficiency of the Advanced Encryption Standard (AES) encrypted circuits. As a case study, the direct memory access (DMA) combined with AES engine and memory controller are implemented as our design-under-test (DUT) using field-programmable gate arrays (FPGA). The results show that our presented ASBUS structure outperforms the AXI-based design for cipher tests. As an example, the 32-bit ASBUS design costs less in terms of hardware resources and achieves higher throughput (1.30 ×) than the 32-bit AXI implementation, and the dynamic energy consumed by the ASBUS cipher test is reduced to 71.27% compared with the AXI test.en_US
dc.language.isoen_USen_US
dc.publisherACM Journal on Emerging Technologies in Computingen_US
dc.subjectAdvanced encryption standard (AES), advanced exensible interface (AXI),bus protocol, filed-programmable gate array (FPGA), system-on-chips (SoC)en_US
dc.subjectHardware → Buses and high-speed links; Application specific integrated circuits;Design modules and hierarchy; Arithmetic and datapath circuits; VLSI system specification and constraints; •Security and privacy → Hardware-based security protocols;en_US
dc.titleImproving AES Core Performance via An Advanced IBUS Protocolen_US
dc.typeArticleen_US


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