An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems
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Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual property (IP) cores. The bus architecture can include a control-bus with a single master, such as a microprocessor, and a data-bus with a single slave, such as DMA.