Xiaokun Yang
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Dr. Xiaokun Yang is currently an Assistant Professor at the College of Science and Engineering, University of Houston, Clear Lake. He received his Ph.D. from the Department of Electrical and Computer Engineering (ECE), Florida International University (FIU), USA in Spring 2016, his dual M.S. from the Department of ECE at FIU and the Department of Software Engineering at Beihang University, China in 2007.
From 2007 to 2012, he has also worked as a Senior ASIC Design/Layout Engineer at Advanced Micro Devices (AMD), China Electronic Corporation (CEC), and PowerLayer MicroSystems (PLM). His chip tape-out experiences include AMD CPUs/APUs (Kabini, Kaveri, Bonaire, Kryptos, and Samara), 802.11 a/b/g/n MIMO mixed-signal SoCs (CEC TL3 and TL5), and PLM high-definition TV (HDTV) SoCs (PLM3K and PLM5K).
Recent Submissions
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Towards High-Throughput and Low-Cost SoC Integration: A Case Study of Scalable Wrapper Designs on FPGAs
(IET Computers & Digital Techniques, 2018) -
Exploiting Energy-Quality (E-Q) Tradeoffs: A Case Study of An Approximate FPGA Design
(IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018) -
Energy Minimization for On-Line Real-Time Scheduling with Reliability Awareness
(Elsevier Journal of Systems and Software, 2017-05)Under current development of semiconductor technology, there is an exponential increase in transistor density on a single processing chip. This aggressive transistor integration significantly boosts the computing performance. ... -
A Case Study of Self-Organization Algorithms for High-Efficiency System-on-Chips Integration
(IEEE Intl. Conf. on Autonomic Computing, 2017-07)As the industry reaps the benefits of Moore's Law and chip designs increase in complexity, System-on-Chip (SoC) integration is becoming intractable with the advent of many new bus or interface protocols. As a case study, ... -
Design of A Bio-Feedback Digital System (BFS) Using 33-Step Training Table for Cardio Equipment
(The 8th Intl. Conference on Applied Human Factors and Ergonomics, 2017-06)In order to efficiently instruct aerobic training on cardio equipment, this paper proposes a secure biofeedback digital system (BFS) with a 33-step training table. As a case study, the system is simulated using Virtex5-110t ... -
Establishing a BLE Mesh Network using Fabricated CSRmesh Devices
(The 2nd ACM/IEEE Symposium on Edge Computing, 2017-10)In this demo we fabricate 4 development boards using the APlix CSR1010 modules and then establish a Bluetooth Low Energy (BLE) mesh network, which is suitable for power-limited and low-complexity IoT applications with ... -
Comparative Power Analysis of An Adaptive Bus Encoding Method on The MBUS Structure
(Journal of VLSI Design, 2017-05)This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO ... -
Design of A Pre-Scheduled Data Bus (DBUS) for Advanced Encryption Standard (AES) Encrypted System-on-Chips (SoCs)
(The 22nd Asia and South Pacific Design Automation Conference, 2017-01)This paper proposes a high efficiency data bus (DBUS) for Advanced Encryption Standard (AES) encrypted system-on-chips (SoCs). Using DBUS, the data sequence can be pre-selected for AES encryption/decryption, so that the ... -
Improving AES Core Performance via An Advanced IBUS Protocol
(ACM Journal on Emerging Technologies in Computing, 2018-01)Security is becoming a de-facto requirement of System-on-Chips (SoC), leading up to a significant share of circuit design cost. In this article, we propose an advanced SBUS protocol (ASBUS), to improve the data feeding ... -
An Advanced Bus Architecture for AES-Encrypted High-Performance Embedded Systems
(2017-10-19)Methods and systems of AES-centric bus architectures and AES-centric state transfer modes are provided. The bus architecture may be implemented on system-on-chip (SoC) devices in conjunction with existing intellectual ...
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