Dr. Xiaokun Yang is currently an Assistant Professor at the College of Science and Engineering, University of Houston, Clear Lake. He received his Ph.D. from the Department of Electrical and Computer Engineering (ECE), Florida International University (FIU), USA in Spring 2016, his dual M.S. from the Department of ECE at FIU and the Department of Software Engineering at Beihang University, China in 2007.
From 2007 to 2012, he has also worked as a Senior ASIC Design/Layout Engineer at Advanced Micro Devices (AMD), China Electronic Corporation (CEC), and PowerLayer MicroSystems (PLM). His chip tape-out experiences include AMD CPUs/APUs (Kabini, Kaveri, Bonaire, Kryptos, and Samara), 802.11 a/b/g/n MIMO mixed-signal SoCs (CEC TL3 and TL5), and PLM high-definition TV (HDTV) SoCs (PLM3K and PLM5K).

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